Complementary metal-oxide-semiconductor (CMOS) devices have become basic devices in integrated circuit (IC) chips. A CMOS device generally includes a p-type metal oxide semiconductor (PMOS) transistor and an n-type metal oxide semiconductor (NMOS) transistor. With development of semiconductor manufacturing technology and for achieving high degree of integration, the CMOS devices are downsized. Consequently, when the CMOS devices are downsized to a certain point, gate length may reach its limitation, which may result in short channel effect. To control the short channel effect and to increase the gate capacitance, high-k dielectric materials have been used to replace conventional low-k silicon oxide. Additionally, metal gate such as aluminum is often used to replace polysilicon gate.
A work function layer may be formed on the gate dielectric layer to adjust threshold voltage of the PMOS and NMOS transistors. The work function layer in a PMOS transistor may be different from the work function layer in an NMOS transistor. Existing methods of forming CMOS devices may include: forming dummy gate structures in regions for forming PMOS and NMOS transistors; removing the dummy gate structure in one of the regions after forming source/drain regions by using the dummy gate structures as a mask; sequentially forming a gate dielectric layer, a work function layer, and a gate electrode layer in this region; and then removing the dummy gate structure in the other region followed by sequentially forming a gate dielectric layer, a work function layer, and a gate electrode layer in the region. Thus, existing methods of forming CMOS devices may include multiple repeating steps of chemical mechanical planarization (CMP) and etching steps, which often leads to errors in dimensions. The resulting CMOS device may operate unstably.
There is a need for processes to provide CMOS devices with improved device performance.